Simulation tool for high-speed communications links

ABSTRACT

A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

BACKGROUND

This relates generally to communications links, and more particularly,to high-speed input-output (I/O) communications links.

A typical communications link includes a transmitter (TX) module, areceiver (RX) module, and a channel that connects the TX module to theRX module. The TX module transmits a serial data bit stream across thechannel to the RX module. Typical high-speed transmit data rates can beas high as 10 Gbps (gigabits per second). Communications links operatingat such high data rates are often referred to as high-speed serial linksor high-speed I/O links.

Circuit simulation tools such as SPICE have been used to simulate thebehavior of communications links. The TX module of a communications linkgenerally includes a driver circuit. SPICE can simulate thedeterministic behavior of the driver circuit, but neglectsnon-deterministic effects such as noise and jitter. Simulating acommunications link at a transistor level using HSPICE can often takehours or days for sufficient test coverage. Such long testing times areundesirable.

Behavior-based simulation tools have been developed to overcome theshortcomings of HSPICE. The pre-emphasis equalization link estimator(PELE) available from Altera Corporation of San Jose, Calif. is anexample of a behavior-based simulation tool. The PELE takes into accountdeterministic characteristics and performs simulations based onone-dimensional statistical modeling (e.g., this tool modelsdeterministic sources that affect the timing but not the amplitude oftransmitted signals) to determine the optimal coefficients for TXpre-emphasis and RX linear equalizations. As a result, the PELE andother conventional behavior-based simulation tools are not always ableto model high-speed communications links such as links that operate atdata rates greater than 10 Gbps as accurately as desired, because randomcharacteristics such as random jitter and noise are not taken intoaccount.

It would therefore be desirable to be able to provide an improvedsimulation tool that can effectively simulate modern high-speedcommunications links.

SUMMARY

A link simulation tool for simulating high-speed communications links isprovided.

A communications link may include transmit (TX) circuitry, receive (RX)circuitry, and a channel that links the TX and RX circuitry. The TXcircuitry may include a TX data module, a TX equalizer, a driver, a TXphase-locked loop (PLL), and a TX oscillator. The TX data module mayfeed data to the TX equalizer. The TX equalizer may output data to thedriver. The TX PLL may receive a reference clock signal from the TXoscillator and may control the timing of the TX data module, TXequalizer, and driver to operate at a desired transmit data rate. Thedriver may output signals with sufficient strength across the channel.

The TX circuitry may include a buffer, an RX equalizer, a register(e.g., a flip-flop), an RX data module, an RX PLL, and an RX oscillator.The TX and RX oscillators may be formed on-chip or off-chip. The buffermay receive signals transmitted over the channel. The buffer may outputsignals to the RX equalizer. The RX equalizer may provide signals to theregister for latching. The flip-flop may feed latched data to the RXdata module. The RX PLL may receive a reference clock signal from the RXoscillator and may include a clock recovery circuit (CRC) that generatesa recovered data clock signal with a recovered clock rate based on thedata rate of the received signals. The RX PLL may control the timing ofthe RX equalizer, the register, and the RX data module to operate at therecovered clock rate.

The TX circuitry, the RX circuitry, and the channel may be representedby respective behavioral models. These behavioral models may includecharacteristic transfer functions, probability density functions (PDF),eye diagrams, etc. The link simulation tool may perform two-dimensionalconvolution and dual domain transformations (e.g., frequency-to-timedomain transformations such as fast Fourier transformations FFT orLaplace transformations) on these characteristic functions to model thebehavior of each link subsystem for each of the communications linksthat are being simultaneously simulated.

The link simulation tool may provide an input screen that presents auser with an opportunity to specify link simulation tool settings. Thelink simulation tool settings input screen allows the user to specify adesired data rate, data pattern file, channel model file, TX/RXsettings, jitter and noise levels, and other settings.

The link simulation tool may also provide a data display screen thatpresents the user with an opportunity to adjust data display settings.The data display screen allows the user to specify a desired plotsetting, test point, target bit error rate (BER), eye plot type, axisscale, etc. The data display screen may display corresponding data plotssuch as a 2D eye diagram, noise and jitter histograms, a 3D BER eyeplot, associated BER plots (e.g., bathtub curves), eye openingcharacteristics (e.g., eye height and eye width), etc.

The link simulation tool may include a link analysis engine thatperforms simulation computations. The link simulation tool may providesimulation results to custom logic or programmable logic design toolsfor use in designing high-speed communication links forapplication-specific integrated circuits (ASIC) or programmable logicdevice (PLD) integrated circuits, respectively.

Further features of the present invention, its nature and variousadvantages will be more apparent from the accompanying drawings and thefollowing detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram of an illustrative communications linkin accordance with an embodiment of the present invention.

FIG. 2 is a schematic diagram of illustrative transmit (TX) circuitry inaccordance with an embodiment of the present invention.

FIG. 3A is a timing diagram of an illustrative data stream generated bya data source in accordance with an embodiment of the present invention.

FIG. 3B is an eye diagram of the illustrative data stream of FIG. 3A inaccordance with an embodiment of the present invention.

FIG. 4A is a timing diagram of an illustrative reference clock signalwith jitter in accordance with an embodiment of the present invention.

FIG. 4B is a probability density function (PDF) of the reference clockjitter shown in connection with FIG. 4A in accordance with an embodimentof the present invention.

FIG. 5 is a transfer function of an illustrative phase-locked loop (PLL)in accordance with an embodiment of the present invention.

FIG. 6 is a probability density function (PDF) of illustrativephase-locked loop (PLL) jitter in accordance with an embodiment of thepresent invention.

FIG. 7 is a transfer function of an illustrative equalizer in accordancewith an embodiment of the present invention.

FIG. 8A is a timing diagram of an illustrative data stream at an inputof a transmit driver in accordance with an embodiment of the presentinvention.

FIG. 8B is an eye diagram of the illustrative data stream of FIG. 8A inaccordance with an embodiment of the present invention.

FIG. 9 is a transfer function of an illustrative transmit driver inaccordance with an embodiment of the present invention.

FIG. 10 is a transfer function of an illustrative transmit packagecircuitry in accordance with an embodiment of the present invention.

FIG. 11A is a timing diagram of an illustrative data stream with jitterand noise at an output of a transmit driver in accordance with anembodiment of the present invention.

FIG. 11B is an eye diagram of the illustrative data stream of FIG. 11Ain accordance with an embodiment of the present invention.

FIG. 12A is a timing diagram of an illustrative data stream with jitterand noise at an input terminal of a channel in accordance with anembodiment of the present invention.

FIG. 12B is an eye diagram of the illustrative data stream of FIG. 12Ain accordance with an embodiment of the present invention.

FIG. 13 is a diagram showing how an illustrative link simulation toolmay be used to design custom logic and programmable logic circuits inaccordance with an embodiment of the present invention.

FIG. 14 is an illustrative input screen that may be presented to providea user with an opportunity to input link simulation tool settings inaccordance with an embodiment of the present invention.

FIGS. 15 and 16 are illustrative data display screens that may bepresented to provide a user with an opportunity to select desireddisplay options in accordance with an embodiment of the presentinvention.

FIG. 17 is an illustrative BER (bit error rate) contour plot inaccordance with an embodiment of the present invention.

FIG. 18 is a diagram of an illustrative programmable logic device (PLD)integrated circuit in accordance with the present invention.

FIG. 19 is a diagram showing how programmable logic device configurationdata is created by a logic design system and loaded into a programmablelogic device to configure the device for operation in a system inaccordance with the present invention.

FIG. 20 is a flow chart of illustrative steps involved in running acommunications link simulation tool of the type shown in FIG. 13 inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

This relates to communications links, and more particularly tosimulation tools that simulate the performance of communications links.

Communications links are commonly used to transport data betweenseparate integrated circuits packages, printed circuit boards, etc. Suchcommunications links may be used to connect integrated circuits thatinclude communications capabilities, such as memory chips, digitalsignal processing circuits, microprocessors, application specificintegrated circuits, programmable logic device integrated circuits,field-programmable gate arrays, application specified standard products,or any other suitable integrated circuit.

Systems in which the links carry high-speed digital signals aretypically among the most challenging to design. A high-speed link might,as an example, carry data at several gigabits per second. A high-speedcommunications link is shown in FIG. 1. Communications link 10 mayinclude transmitter (TX) circuitry such as TX circuitry 62, a channelsuch as channel 66, and receiver (RX) circuitry such as RX circuitry 64.Channel (channel subsystem) 66 may connect TX circuitry 62 to RXcircuitry 64.

TX circuitry 62 may be formed on a first integrated circuit while RXcircuitry 64 may be formed on a second integrated circuit (as anexample). The first and second integrated circuits may be mounted on aprinted circuit board (PCB). Channel 66 (e.g., conductive traces on thePCB, wires, copper cables, etc.) may be used to connect the first andsecond integrated circuits. The first integrated may use TX circuitry 62to transmit data to RX circuitry 64 in the second integrated circuitrythrough channel 66. If desired, more than one channel may be used tolink TX circuitry 62 to RX circuitry 64.

This example is merely illustrative. Communications link 10 of the typedescribed in connection with FIG. 1 may be used provide data transportbetween integrated circuits, printed circuit boards, circuits within asingle integrated circuit, etc.

TX circuitry 62 may include a TX data source such as data source 68, aTX equalizer such as equalizer 70, a TX driver such as driver 78, a TXphase-locked loop (PLL) such as PLL 72, and a TX oscillator such asoscillator 74. Data source 68 may provide data to be transmitted. Forexample, data source 68 may be a parallel-in serial-out (PISO) datacircuit or a serializer. In this example, data source 68 may provide TXcircuitry 62 with a serial data bit stream for transmission.

Equalizer 70 may receive data from data source 68. Equalizer 70 may beused to provide high-frequency and direct signal level boosting tocompensate for high-frequency signal loss commonly seen in high-speedserial links (e.g., losses in copper-based channels that exhibitundesired low-pass transfer characteristics that result in signaldegradation at high data rates) or to enhance signal to noise ratio(SNR) in scenarios in which uncorrelated noise such as crosstalk ispresent. Equalizer 70 may implement linear equalization schemes such asfinite impulse response (FIR) and feed forward equalization (FFE)schemes or nonlinear adaptive equalization schemes such as infiniteimpulse response (IIR) or decision feedback equalization (DFE) schemes(as examples).

Equalizer 70 may output equalized data to driver 78. Driver 78 may havean output that is connected to a first terminal of channel 66. Theoutput of driver 78 may have an output differential resistance of 10Ohms to provide impedance matching with channel 66 (e.g., the firstterminal of channel 66 has an input differential resistance of 10 Ohms).Impedance matching may provide maximum signal power transfer from driver78 to channel 66 and may eliminate signal reflection. Driver 78 may beused to provide sufficient drive strength to drive the data streamacross channel 66.

PLL 72 may receive reference clock signal REF CLK from oscillator 74.Oscillator 74 may be an on-chip crystal oscillator (as an example).Signal REF CLK may be provided from an off-chip oscillator, if desired.PLL 72 may produce a desired transmit data clock signal over line 76 tocontrol data source 68 and equalizer 70. The data clock signal may havea transmit clock rate that is an integer multiple of the clock rate ofreference clock signal REF_CLK. For example, consider a scenario inwhich signal REF_CLK has a clock rate of 3 GHz. The data clock signalmay have a transmit clock rate of 6 GHz, 9 GHz, 12 GHz, 18 GHz, etc. TXcircuitry 62 may transmit the serial data bit stream with a transmitdata rate that is equivalent to the clock rate of the data clock signalgenerated by PLL 72. For example, consider a scenario in which thetransmit clock rate is 15 GHz. In this type of scenario, driver 78,which is controlled by the corresponding transmit data clock signal,will transmit data at a transmit data rate of 15 Gbps. If desired, datacan be transmitted at 30 Gbps if both rising and falling edges of thedata clock signal are used to clock the data in half-rate architectures(as an example).

Channel 66 may have a second terminal that is connected to RX circuitry64. RX circuitry 64 may include an RX buffer such as buffer 80, an RXequalizer such as equalizer 82, a register (e.g., a flip-flop) such asregister 84, an RX data destination such as data module 86, an RX PLLsuch as PLL 88, and an RX oscillator such as oscillator 92.

The second terminal of channel 66 may be connected to an input of buffer80. Buffer 80 may receive data from channel 66. Buffer 80 may have aninput differential resistance of 10 Ohms for impedance matching (e.g.,the second terminal of channel 66 has an output differential resistanceof 10 Ohms). Buffer 80 may provide additional pre-amplification for thereceived data, if desired.

Buffer 80 may output the received data to equalizer 82. Equalizer 82 mayprovide further high-frequency boosting or direct signal level boostingto compensate for any additional undesired high-frequency signal loss.Equalizer 82 may output the received data that has been equalized toregister 84. Register 84 may latch desired data and may output thedesired data to data source 84. Data source 86 may be a serial-inparallel-out (SIPO) or a de-serializer data circuit (as an example). Inthis example, data source 86 may convert the serial data bit stream toparallel data for later processing.

Buffer 80 may provide the received data to PLL 88. PLL 88 may include aclock recovery circuit (CRC) such as CRC circuit 90. PLL 88 may receivelocal reference clock signal REF_CLK′ from oscillator 92. Oscillator 92may be an on-chip crystal oscillator (as an example). Signal REF_CLK′may be generated by an off-chip oscillator, if desired. PLL 72 may useCRC 90 to generate a recovered data clock signal based on the data rateof the received data.

For example, consider a scenario in which the data rate of the receiveddata is 16 Gbps and the clock rate of signal REF_CLK′ is 2 GHz. PLL 72may generate a recovered data clock signal on line 77 that has arecovered clock rate that matches the data rate of the received data.The recovered data clock in this example may therefore exhibit arecovered clock rate of 16 GHz that matches the received data rate of 16Gbps. The recovered data clock signal is provided over line 77 tocontrol equalizer 82, register 84, and data source 86 to process data atthe recovered clock rate.

All the components (e.g., equalizers 70 and 82, driver 78, channel 66,and buffer 80) in the data path indicated by dotted line 69 may beimplemented using differential architecture. For example, equalizers 70and 82 may have differential inputs and differential outputs instead ofsingle-ended inputs and outputs, and the data transmitted over channel66 may be in the form of differential signals.

Communications link system 10 may be simulated using a link simulationtool. Each link subsystem (e.g., TX circuitry 62, channel 66, or RXcircuitry 64) may be simulated using a computer-aided design (CAD)simulation tool that captures the behaviors of each subsystem of theentire link system through the use of behavioral (subsystem) models. Forexample, first and second subsystem models may be used to model thebehaviors of circuitry 62 and 64, respectively. A third subsystem modelmay be used to model passive characteristics of channel subsystem, 66.Additional behavior models may be used to model more than one channel(e.g., for multi-channel link systems), if desired. If desired, anynumber of link systems 10 may be simultaneously simulated using the linksimulation tool.

The first, second, and third subsystem models can be used to simulatethe behavior of link system 10 according to an overall link metric. Theoverall link metric may be a bit error rate (BER), as an example. Thebit error rate is defined as the ratio of the number of error bits(e.g., received bits that have been corrupted by noise, jitter,interference, etc.) to the total number of transmitted bits within agiven time period.

For example, consider a scenario in which two terabits were transmittedwithin five seconds. There may be two incorrect bits that weretransferred erroneously. The BER is therefore 10⁻¹² (2 divided by2*10¹²). For high-speed communications links such as link 10, it may bedesirable to set the BER to 10⁻¹² or smaller (e.g., 10⁻¹², 5*10⁻¹⁴,2.8*10⁻¹⁵, etc.).

The link simulation may be used to calculate partial link metrics atdifferent test points in link system 10. The test points refer toparticular points of interest in communications link 10. For example, atest point TP1 may be located at the output of driver 78, another testpoint TP2 may be located at the input of buffer 80, TP3 may be locatedat the output of buffer 80, and TP4 may be located at the output ofequalizer 82, as shown in FIG. 1. If desired, any number of test pointsmay be placed at any number of points in link system 10.

The behavioral model of TX circuitry 62 may be implemented usingsoftware abstractions of the actual hardware in system 10. For example,TX circuitry 62 may be abstracted into a schematic representation (asshown in FIG. 2) in which each of the components is modeled by anindividual characteristic function (e.g., a transfer function, aprobability density function, etc.).

Each connection in FIG. 2 may indicate that two connected componentsinteract with each other and that their respective characteristicfunctions are related. Data source 68 may be connected to equalizer 70through line 96. Equalizer 70 may be connected to driver 78 through line98. Oscillator 92 may provide signal REF_CLK to PLL 72 over line 110.PLL 72 may provided a transmit data clock signal to equalizer 70 overline 76. Driver 78 may be supplied by positive power supply line 100(e.g., a line that is driven to positive power supply voltage Vcc) andby ground power supply line 102 (e.g., a line that is driven to zerovolts or Gnd). Driver 78 may be connected to a TX circuitry package suchas TX circuitry package 94. There may not actually be a discretepackaging component in TX circuitry 62. Package 94 merely serves torepresent a low-pass characteristic of an integrated circuit packagethat contains circuitry 62 and that is used for mounting TX circuitry 62onto a printed circuit board. Schematically, package 94 is connected tochannel 66 through line 106. The connections (i.e., lines) in FIG. 2 mayrepresent simulated data flow paths.

It may be helpful to examine the individual characteristic functions atthe outputs of data source 68 (as indicated by point A), equalizer 70(as indicated by point B), driver 78 (as indicated by point C), package94 (as indicated by point D), oscillator 92 (as indicated by point E),and PLL 72 (as indicated by point F). The mechanism through which thesecharacteristic functions may be combined to simulate an overall linksubsystem behavior may sometimes be referred to as convolution (e.g.,two-dimensional convolution in the time domain or in the frequencydomain).

At point A, a signal such as v_(A)(t) may be generated by data module68. Signal v_(A)(t) may represent a possible data bit stream (e.g.,0100010100) that varies as a function of time, as shown in FIG. 3A.Signal v_(A)(t) may be a differential signal that is centered at zerovolts (as an example).

FIG. 3B shows an eye diagram such as eye diagram f_(A)(t,v). Eye diagramf_(A)(t,v) may be a two-variable function that is dependent on time andvoltage (e.g., time and voltage correspond to the two axes of the eyediagram). Eye diagram f_(A)(t,v) may be formed by repetitively samplingsignal v_(A)(t) at regular time intervals and by overlaying the sampledsignals. For example, waveform 112 may represent samples having adifferential value of “1” while waveform 114 may represent sampleshaving a differential value of “0.” Diagram f_(A)(t,v) represents anideal eye pattern, because the transitions of waveforms 112 and 114 arevertical (e.g., infinite slope) and because no variation in time (e.g.,jitter) or voltage (e.g., noise) is present to distort the eye pattern.

At point E, reference clock signal REF_CLK is generated by oscillator92. Signal REF_CLK may be a square wave clock signal having 50% dutycycle (see, e.g., FIG. 4A). Signal REF_CLK may exhibit more or less than50% duty cycle, if desired. Oscillator 92 may not produce an idealsquare wave. For example, oscillator 92 may generate a square wavehaving random jitter (e.g., random variation in the time domain) thatcauses the rising/fallings edges of signal REF_CLK to shift in time, asindicated by Δt in FIG. 4A.

The random jitter of signal REF_CLK may be characterized by aprobability density function (PDF) such as probability density functionf_(OSC)(t) of FIG. 4B. In general, a probability density function plotsthe relative likelihood that a random variable with a particular valuewill occur. PDF f_(OSC)(t) plots the probability for a given jitter tooccur as a function of time. For example, PDF f_(OSC)(t) has a peak thatcorresponds to nominal jitter Δt_(NOM). Signal REF_CLK may thereforeexhibit random jitter with a value that is approximately equal tonominal jitter Δt_(NOM) for a majority of the time (e.g., peak in PDFcorresponds to highest probable occurrence). Jitter values that deviatefar from the nominal jitter may still occur but with relatively lessprobability. The random jitter of signal REF_CLK may therefore beuniquely characterized by PDF f_(OSC) (t).

PLL 72 may be characterized by a transfer function such as transferfunction |H_(PLL)(f)|, as shown in FIG. 5. Transfer function|H_(PLL)(f)| plots the magnitude response of PLL 72 as a function offrequency. Transfer function |H_(PLL)(f)| may have a low-passcharacteristic with a finite bandwidth BW. A phase response may be usedin conjunction with magnitude response |H_(PLL)(f)| to characterize PLL72, if desired.

The behavior at the output of PLL 72 may be determined by convolving PDFf_(OSC)(t) with transfer function |H_(PLL)(f)|. Convolution is atechnique that involves integrating the product of two functions afterone is reversed and shifted in the time domain. Convolution takes twofunctions as inputs and outputs a third function that can be viewed as across-correlated version of the two functions.

Generally, convolution of two functions requires that the two functionsbe either both in the time domain or both in the frequency domain. In ascenario in which the two functions are in different domains,transformations such as the Fourier transform (e.g., fast Fouriertransform FFT) or the inverse Fourier transform (e.g., inverse fastFourier transform IFFT) may be used to convert a function from timedomain to frequency domain or from frequency domain back to time domain,respectively. If desired, transformations such as the Laplace transformor the inverse Laplace transform may also be used. Superior throughputcan be achieved relative to the conventional SPICE simulation method bythe use of dual domain (e.g., time and frequency) operation and fasttransformations between them.

The output characteristic of PLL 72 (e.g., point F) may be representedby time function f_(F)(t) and the corresponding PDF, as shown in FIG. 6.In simulation, f_(F)(t) may be calculated by convolving time functionf_(OSC)(t) with h_(PLL)(t) (i.e., an inverse Fourier transform of|H_(PLL)(f)|), as shown in equation 1.f _(F)(t)=f _(OSC)(t)*h _(PLL)(t)  (1)In equation 1, the symbol “*” represents the convolution function. Ifthe PLL transfer function exhibits peaking, the corresponding outputjitter will be amplified at the frequency at which the peaking occurs.

Equalizer 70 may be characterized by transfer function H_(EQ)(f), asshown in FIG. 7. Equalizer 70 may be used to provide high-frequencyboosting (region 71) to compensate for any undesired high-frequencysignal loss. Equalizer 70 may have a finite bandwidth BW′ and mayattenuate high-frequency signals beyond bandwidth BW′.

A data signal such as differential signal v_(B)(t) may be present at theoutput of equalizer 70 (e.g., point B), as shown in FIG. 8A. Ideal inputsignal v_(A)(t) of FIG. 3A may acquire undesirable jitter as it ispassed through equalizer 70, because equalizer 70 is controlled by PLL72, which has random jitter characteristics.

FIG. 8B shows eye diagram f_(B)(t,v) when signal v_(B)(t) is sampled andoverlaid over one bit period. The eye pattern of f_(B)(t,v) has at leasttwo non-idealities. First, jitter may cause the eye to become narrower(e.g., an eye width EW is reduced) in the time domain. Second, thelimited bandwidth of equalizer 70 and PLL 72 may result in finiterise/fall times that also degrade eye width EW. In simulation, eyediagram f_(B)(t,v) may be computed by convolving eye diagram f_(A)(t,v)with PDF f_(F)(t) and with h_(EQ)(t) (e.g., a fast Fourier transform ofH_(EQ)(f)), as shown in equation 2.f _(B)(t,v)=f _(A)(t,v)*f _(F)(t)*h _(EQ)(t)  (2)

FIGS. 9 and 10 show transfer functions (i.e., magnitude frequencyresponses) |H_(DR)(f)| and |H_(PKG)(f)| of driver 78 and package 94,respectively. Transfer functions |H_(DR)(f)| and |H_(PKG)(f)| mayrepresent magnitude responses as a function of frequency and may bothhave low-pass characteristics. Transfer functions |H_(DR)(f)| and|H_(PKG)(f)| may have different bandwidths and may roll off (e.g.,decrease in magnitude as frequency increases) at different rates.

As shown in FIG. 11A, a differential signal such as signal v_(C)(t) maybe present at the output of driver 78 (e.g., point C). Signal v_(B)(t)of FIG. 8A may acquire undesirable noise (e.g., variation in amplitudein the voltage domain as indicated by noise Δv) as it is passed throughdriver 78. Driver 78 is powered by power supply lines 100 and 102 thatmay suffer from power supply variation and noise (e.g., variation andnoise in supply voltages Vcc and Gnd). Random noise generated in thisway may be characterized by noise function f_(DR)(v).

FIG. 11B shows eye diagram f_(C)(t,v) when signal v_(C)(t) is sampledand overlaid with itself. The eye pattern of f_(C)(t,v) is furtherdegraded. First, noise may cause the eye to become shorter (e.g., an eyeheight EH is reduced) in the voltage domain. Second, the limitedbandwidth of driver 78 may result in longer rise/fall times that furtherdegrade eye width EW. In simulation, eye diagram f_(C)(t,v) may becalculated by convolving eye diagram f_(B)(t,v) with h_(DR)(t) (e.g., aninverse Fourier transform of |H_(DR)(f)|), and noise function f_(DR)(v),as shown in equation 3.f _(C)(t,v)=f _(B)(t,v)*h _(DR)(t)*f _(DR)(v)  (3)

As shown in FIG. 12A, a signal such as differential signal v_(D)(t) maybe present at the output of package 94 (e.g., point D). The output ofpackage 94 corresponds to the interface that connects TX circuitry 62 tochannel 66. Signal v_(D)(t) of FIG. 12A may be further degraded by thelow-pass characteristic of package 94.

FIG. 12B shows eye diagram f_(D)(t,v) when signal v_(D)(t) is sampledand overlaid on itself. The limited bandwidth of package 78 may resultin even longer rise/fall times that further close the eye pattern (i.e.,reduce eye width EW). In simulation, eye diagram f_(D)(t,v) may bedetermined by convolving eye diagram f_(C)(t,v) with h_(PKG)(t) (e.g.,an inverse fast Fourier transform of |H_(PKG)(f)|), as shown in equation4.f _(D)(t,v)=f _(C)(t,v)*h _(PKG)(t)  (4)

Signals shown in eye diagram f_(D)(t,v) may represent the actual signalsthat are provided to channel 66 for transmission to RX circuitry 64.

The link simulation tool may perform convolution calculations of thetype shown in equations 1-4 to model the behavior of TX circuitry 62.The link simulation tool may perform two-dimensional (2D) convolution(e.g., convolution with two independent variables). This allowsprocessing of model functions that are dependent on both time andvoltage. Performing 2D convolution for deterministic and random signalcomponents using this approach may achieve superior accuracy overconvention 1D convolution methods.

FIGS. 2-12 and equations 1-4 merely serve to illustrate one possibleapproach of modeling TX circuitry 64. RX circuitry 64 may be modeledwith this type of approach using a schematic setup of the type shown inFIG. 2 and using 2D convolution computations of the type shown inequations 1-4. If desired, all the data signals may be single-ended.

Channel 66 generally does not introduce random noise or jitter, becauseit only includes passive elements. Channel 66 may therefore berepresented by a transfer function having a low-pass characteristic.

The link simulation tool may compute the behavior of communications link10 as a system by convolving the results of each of the subsystems oflink 10 (e.g., by convolving the characteristic functions of circuitry62, circuitry 64, and channel 66). Convolving the characteristicfunctions in this way produces an overall link characteristic functionthat can be used to determine the performance of the entire link system.

As shown in FIG. 13, a link simulation tool such as link simulation tool118 may be run on computing equipment such as computing equipment 116.Link simulation tool 118 may include a link analysis engine such as linkanalysis engine 120. Link analysis engine may be used to perform 2Dconvolution computations, BER calculations, and other desiredoperations. Computing equipment 116 may be based on any suitablecomputer or network of computers. With one suitable arrangement,computing equipment 116 includes a computer that has sufficientprocessing circuitry and storage to run link simulation tool 118 andstore corresponding simulation results. Equipment 116 may have a displayand user input interface for gathering user input and displayingmodeling results to a user.

Link simulation tool 118 may provide information to a custom logicdesign tool such as custom logic design tool 122, a programmable logicdesign tool such as programmable logic design tool 126, or othersuitable computer-aided design tools. Based on the information providedby link simulation tool 118, design tools 122 and 126 may be used toprovide design parameters to help design high-speed I/O communicationslinks in application-specific integrated circuits 124 and programmablelogic devices 128, respectively.

An illustrative input screen 130 that may be provided to a systemdesigner or other user by simulation tool 118 is shown in FIG. 14.Screen 130 may provide the user with an opportunity to input linksimulation tool settings. Screen 130 may be displayed on a computermonitor or other I/O device (computing equipment 116).

Input screen 130 may have an input region such as settings parametersinput region 132. Input region 132 may allow the user to choose tomanually edit or load from a file the remaining link simulation toolsettings. A drop-down menu or other interface may be invoked by clickingon edit option 133 to allow the user to select between availableoptions.

Input screen 130 may have another input region such as global settinginput region 134. Input region 134 may allow the user to specify adesired data rate for the communications link and to specify a desiredbrowse pattern file (e.g., a file that includes the desired data bitsequence for transmission). Input region 134 may include fillable textboxes or other input options that allow the user to specify desiredglobal settings. In the example of FIG. 14, the user has specified thatlink 10 must transmit data at a data rate of 8.5 Gbps and that filePRBS7.TXT is to be used. File PRBS7.TXT may be a text file that includesa pseudorandom binary sequence of bits for use in a simulation (as anexample).

Input screen 130 may have another input region such as channel settinginput region 136. Input region 136 may allow the user to specify adesired channel file (e.g., a file that includes parameters that modelthe passive behaviors of a particular channel). In the example of FIG.14, the user has specified in a fillable text box that channel fileCH3.S4P is to be used to simulate channel 66.

Input screen 130 may have another input region such as TX setting inputregion 138. Input region 138 may allow the user to specify a desiredoutput differential voltage (VOD) level at the output of driver 78. ThisVOD level may represent a peak-to-peak voltage difference between a hightransmit signal value and a low transmit signal value (see, e.g., eyeheight EH of FIG. 12B). Higher VOD levels translate to stronger signals(e.g., signals having larger amplitudes) at the cost of increased powerconsumption at the transmitter. In the example of FIG. 14, the user hasspecified in a fillable text box a VOD level of 600 mV.

Input screen 130 may have another input region such as BER eye/contourinput region 140. Input region 140 may allow the user to specify desiredrandom jitter (RJ), random noise (RN), and other jitter and noisecomponent levels (e.g., duty cycle distortion, etc.) at the transmitterand at the receiver. The RJ levels may be supplied in units of time(e.g., picoseconds) while the RN levels may be supplied in units ofsignal amplitude (e.g., millivolts). The random jitter and noise levelsdirectly affect the eye diagram and associated BER plots at any pointwithin link 10. In the example of FIG. 14, the user has specified infillable text boxes that a TX RJ level of 1.5 ps, a TX RN level mV, anRX RJ level of 1.2 ps, and an RX RN level of 2.5 mV be used insimulations.

These input regions on input screen 130 are merely illustrative.Additional input regions to specify link simulation tool 118 with moresettings or options may be incorporated, if desired.

The user may click on a menu button such as button 141 to direct linksimulation tool 118 to simulate the operation of communications link 10based on the link simulation tool settings specified on input screen130. After simulation is complete, the user may click on a menu buttonsuch as data display button 143 to display another screen such as datadisplay screen 142 of FIG. 15.

Display screen 142 of FIG. 15 may have an input region such as datasetting input region 144. Input region 144 may allow the user to specifya desired data source file, plot setting, test point, and target BER.The data source file may be an output file containing correspondingsimulation results. The plot setting reflects the type of plot that isused to display the simulation results. The desired test point refers toa particular point of interest in communications link 10. Waveforms orplots that are displayed on display screen 142 may be specific to theselected test point. In the example of FIG. 15, the user has specifiedin fillable text boxes that data source file DATA.MAT be used, thatwaveforms at test point TP4 (e.g., at the output of equalizer 82) shouldbe displayed using an “eye PDF” plot type, and that link 10 exhibit aBER of less than 10⁻¹².

Display screen 142 may have another input region such as plot optionsinput region 146. Input region 146 may allow the user to specify adesired plot type and time axis scale. In the example of FIG. 15, theuser has specified in drop-down menus that overlaid lines be used as thedesired plot type (e.g., a plot type that is used to display 2D eyediagrams) and that the time axis scale be in units of picoseconds (ps).

Display screen 142 may have another input region such as actions inputregion 148. Input region 148 may have menu buttons such as plot resultsbutton 150 and link settings button 152. Selecting plot results button150 may direct display screen 142 to display waveforms/plotscorresponding to the desired data settings and plot options specified ininput regions 144 and 146. Selecting link settings button 152 may launchinput screen 130 to give the user the opportunity to alter any linksimulation tool settings as desired.

Display screen 142 may display an eye diagram such as eye diagram 150.Eye diagram 150 may be a 2D plot (e.g., plotting amplitude in mV versustiming in ps) with overlaid waveforms at test point TP4 (as an example).

Because the plot setting of “eye PDF” is selected in this example,display screen 142 may plot probability density functions such as noisehistogram 152 and jitter histogram 154. Noise histogram 152 may plot therelative occurrence of reference voltage at a center strobe timing(i.e., zero ps). The peaks of the noise histogram plot correspond tonominal amplitudes of the transmitted signals at TP4. For example, thenominal signal amplitudes are 120 mV and −120 mV, as shown in FIG. 15.The spread or deviation from these peaks indicates the amount of noisevariation that affects the amplitude of the transmitted signals.

Similarly, jitter histogram 154 plots the relative occurrence ofcrossing points at a center reference voltage (i.e., zero volts). Thepeaks of the jitter histogram plot correspond to nominal crossing points(e.g., where the waveforms intersect with zero reference voltage) atTP4. For example, the nominal strobe timing crossing points are at −75ps and 75 ps, as shown in FIG. 15. The spread or deviation from thesepeaks indicates the amount of jitter variation that affects the timingconstraints of the transmitted signals.

Data display screen 142 may include a region such as eye opening region156. Region 156 may allow the user to specify a desired voltage valueand a desired strobe time for determining eye width EW and eye heightEH, respectively. In the example of FIG. 15, the user has chosen tomeasure eye width EW and height EH at the zero crossing point (i.e., 0mV) and at the center strobe time (i.e., 0 ps). Simulation tool 118 hasdetermined that the corresponding maximum eye width EW is 126 ps and thecorresponding maximum eye height EH is 151 mV (as examples). The usermay specify other reference values to determine EW and EH, if desired.

In another suitable arrangement, data display screen 142 may beconfigured to display a 3-dimensional BER plot and other associatedplots, as shown in FIG. 16. For example, the user may opt to view an eyeCDF (cumulative density function) plot setting with a 3D eye plot typeand with a logarithmic (log) scale at test point TP3 (e.g., at the inputof buffer 80).

Display screen 142 may therefore display a BER eye plot such as BER plot158. BER plot 158 may be a 3D plot (e.g., plotting BER values on a logscale against amplitude and timing) at test point TP3 (as an example). ABER contour plot such as BER contour plot 159 may be formed byprojecting downwards the 3D BER plot onto the 2D plane of amplitudeversus time. Each horizontal cross-section of the BER plot correspondsto a particular BER value and a separate contour line of plot 159.

Because the plot setting of eye CDF is selected in this example, displayscreen 142 may plot cumulative density functions (CDF) such as plots 160and 162. Curves in plots 160 and 162 may sometimes be referred to asbathtub curves. Plot 160 may plot BER (in log scale) as a function ofreference voltage. In general, the BER is minimized at the zero crossingpoint (i.e., zero volts), because the crossing point corresponds to themaximum eye opening (width) with respect to the time axis. BER willincrease at higher reference voltages, because of the random noise inthe transmitted signals. In general, it is desirable for bathtub curves161 to be far away from each other, because a wide bathtubcharacteristic indicates a larger eye opening for a respective axis(e.g., the time axis).

Plot 162 may plot BER as a function of strobe timing. In general, theBER in plot 162 is minimized at the center strobe timing (i.e., zerops), because for a majority of the time, the center strobe timingcorresponds to the maximum eye height in the voltage/amplitude domain.BER will increase at more distant strobe timing (i.e., timing fartheraway from zero ps), because of random jitter that is inherent to thetransmitted signals. In the example of FIG. 16, bathtub curves 163 arerelatively wider than curves 161, indicating that random noise has amore detrimental effect than the impact of random jitter in closing theeye diagram.

In the example of FIG. 16, simulation tool 118 has determined that thecorresponding maximum eye width EW is 44 ps and the correspondingmaximum eye height EH is 50 mV (see, e.g., eye opening region 156).These eye opening values are smaller than those shown in FIG. 15,because signals at the input of equalizer 82 (e.g., at TP3 beforeequalization) are more distorted than signals at the output of equalizer82 (e.g., at TP4 after equalization).

As shown in FIG. 17, data display screen 142 may also be used to displayBER contour plot 159 using a 2D eye plot type. Contour plot 159 plotsreference voltage versus time (i.e., strobe timing). Each contour linesuch as line 164, 166, or 168 corresponds to an eye opening having arespective BER value. In general, same contour lines with smalleropenings have higher BER values (e.g., more degraded signals) while samecontour lines with wider openings have lower BER values. For example,lines 164, 166, and 168 may correspond to contour curves with BER valuesof 10⁻¹², 10⁻¹⁴, and 10⁻¹⁶, respectively.

Link simulation tool 118 may be used to design a communications link ina programmable logic device integrated circuit. An illustrativeprogrammable logic device 10 is shown in FIG. 18. Programmable logicdevice 10 may have input/output circuitry 12 for driving signals off ofdevice 10 and for receiving signals from other devices via input/outputpins 14. Programmable logic 18 may include combinational and sequentiallogic circuitry and may be interconnected using fixed and programmableinterconnects 16.

Programmable logic devices contain programmable elements 20. In general,programmable elements 20 may be based on any suitable programmabletechnology, such as fuses, antifuses, electrically-programmableread-only-memory technology, random-access memory cells, etc.

Programmable elements 20 each provide a corresponding static controloutput signal that controls the state of an associated logic componentin programmable logic 18. The output signals are typically applied tothe gates of metal-oxide-semiconductor (MOS) transistors.

An illustrative system environment for a programmable logic device 10 isshown in FIG. 19. Programmable logic device 10 may be mounted on a board36 in a system 38. Programmable logic device 10 may receiveconfiguration data from programming equipment or from any other suitableequipment or device. In the example of FIG. 19, programmable logicdevice 10 is the type of programmable logic device that receivesconfiguration data from an associated integrated circuit 40. With thistype of arrangement, circuit 40 may, if desired, be mounted on the sameboard 36 as programmable logic device 10. The circuit 40 may be anerasable-programmable read-only memory (EPROM) chip, a programmablelogic device configuration data loading chip with built-in memory(sometimes referred to as a configuration device), or any other suitabledevice. When system 38 boots up (or at another suitable time), theconfiguration data for configuring the programmable logic device may besupplied to the programmable logic device from device 40, as shownschematically by path 42. The configuration data that is supplied to theprogrammable logic device may be stored in the programmable logic devicein its configuration random-access-memory elements 20.

System 38 may include processing circuits 44, storage 46, and othersystem components 48 that communicate with device 10. The components ofsystem 38 may be located on one or more boards such as board 36 or othersuitable mounting structures or housings. As shown in the example ofFIG. 19, communications paths are used to interconnect device 10 toother components. For example, communications path 37 is used to conveydata between an integrated circuit 39 that is mounted on board 36 andprogrammable logic device 10. Communications paths 35 and 50 are used toconvey signals between programmable logic device 10 and components 44,46, and 48.

Configuration device 40 may be supplied with the configuration data fordevice 10 over a path such as path 52. Configuration device 40 may, forexample, receive the configuration data from configuration data loadingequipment 54 or other suitable equipment that stores this data inconfiguration device 40. Device 40 may be loaded with data before orafter installation on board 36.

It can be a significant undertaking to design and implement a desiredlogic circuit in a programmable logic device. Logic designers thereforegenerally use logic design systems based on computer-aided-design (CAD)tools to assist them in designing circuits. As shown in FIG. 19, theconfiguration data produced by a logic design system 56 may be providedto equipment 54 over a path such as path 58. Equipment 54 provides theconfiguration data to device 40, so that device 40 can later providethis configuration data to the programmable logic device 10 over path42. System 56 may be based on one or more computers and one or moresoftware programs. In general, software and data may be stored on anycomputer-readable medium (storage) in system 56.

In a typical scenario, logic design system 56 is used by a logicdesigner to create a custom circuit design based on simulation resultsfrom simulation tool 118 (and, if desired, can be used to implement thefunctions of link simulation tool 118). System 56 produces correspondingconfiguration data which is provided to configuration device 40. Uponpower-up, configuration device 40 and data loading circuitry onprogrammable logic device 10 is used to load the configuration data intothe CRAM cells 20 of device 10. Device 10 may then be used in normaloperation of system 38.

FIG. 20 shows illustrative steps involved in using link simulation tool118 to simulate communications link 10. At step 170, tool 118 mayprovide a user with an opportunity to specify link system simulationtool settings (e.g., tool 118 may prompt a user to input a desired linkdate rate, data pattern file, channel model, TX/RX settings, BERsettings, etc.).

At step 172, link simulation tool 118 may run link analysis engine 120to produce simulation results. The running of link analysis engine 120may involve performing mathematical computations (e.g., 2D convolutionoperations, fast Fourier transforms, etc.), generating and displayingplots (e.g., eye diagrams, BER plots, noise/jitter histograms, etc.),and storing results in storage circuitry in the computing equipment thatruns tool 118 (as examples).

Link simulation tool 118 may generate simulation results. The simulationresults may be displayed on a screen such as the data display screenshown in FIGS. 15 and 16. The simulation results may or may not satisfydesign criteria depending on the requirements of the systems designer(step 180). If the simulated results (e.g., eye width, eye height,jitter/noise histograms, BER contour plots, etc.) does not satisfydesign criteria, processing may loop back to step 170 so that the designcan be refined, as indicated by path 182.

If the simulation results satisfy design criteria, link simulation tool118 may supply output results to ASIC (application-specific integratedcircuit) or PLD (programmable logic device) CAD tools such as system 56.These tools (e.g., system 56) may then produce configuration data, masksfor an ASIC, etc. (step 184). Configuration data may be loaded onto aprogrammable integrated circuit such as programmable logic deviceintegrated circuit 10 of FIG. 18 (step 186). A programmable integratedcircuit configured in this way will exhibit the desired link performancespecified by the designer using link simulation tool 118 and system 56.

Link simulation tool 18 may be used to simultaneously simulate anynumber of communications links. Link simulation tool 118 serves as ageneric, end-to-end statistical link simulator that can be used todesign any desired high-speed communications link architecture. Linksimulation tool 118 may provide coverage of any desired signaldistortion/impairment mechanism (e.g., lossy medium, reflection, crosstalk, interference, etc.) that affects overall link performance. Usinglink simulation tool 118 to design a high-speed communications linkhelps provide accurate and rapid link system architecture evaluation andselection results and helps provide fast performance and costoptimization results for link system and subsystem design.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention.

What is claimed is:
 1. A method of simulating a communications linkusing a link simulation tool implemented on computing equipment, whereinthe communications link includes respective link subsystems and whereinthe link subsystems in the communications link are represented bysubsystem models in the link simulation tool, the method comprising:performing two-dimensional convolution operations on the subsystemmodels to determine link performance for the communications link usingthe link simulation tool, wherein the two-dimensional convolutioncomprises convolution on expressions that are a function of time andvoltage, wherein the link subsystems comprise a transmitter subsystemthat is represented by a transmitter subsystem model in the linksimulation tool, and wherein performing the two-dimensional convolutionoperations comprises performing two-dimensional convolution operationswith the transmitter subsystem model.
 2. The method defined in claim 1,wherein the link subsystems comprise a receiver subsystem that isrepresented by a receiver subsystem model in the link simulation tooland wherein performing the two-dimensional convolution operationsfurther comprises performing two-dimensional convolution operations withthe receiver subsystem model.
 3. The method defined in claim 2, whereinthe transmitter and receiver subsystems comprise transmitter andreceiver subsystem components each of which is represented by arespective one of a plurality of characteristic functions, the methodfurther comprising: performing two-dimensional convolution operations onthe plurality of characteristic functions.
 4. The method defined inclaim 3, wherein the transmitter subsystem components of thecommunications link comprise components including: a first equalizer, afirst phase-locked loop, a first oscillator, and a driver, and whereinthe receiver subsystem components comprise components including: abuffer, a second equalizer, a second phase-locked loop, and a secondoscillator.
 5. The method defined in claim 4, wherein performing thetwo-dimensional convolution operations on the characteristic functionscomprises: convolving the characteristic functions of the firstequalizer, the first phase-locked loop, the first oscillator, and thedriver to produce the transmitter subsystem model; and convolving thecharacteristic functions of the buffer, the second equalizer, the secondphase-locked loop, and the second oscillator to produce the receiversubsystem model.
 6. The method defined in claim 1, wherein the linksubsystems comprise a channel subsystem that is represented by a channelsubsystem model in the link simulation tool and wherein performing thetwo-dimensional convolution operations further comprises performingtwo-dimensional convolution operations with the channel subsystem model.7. A method of simulating a communications link using a link simulationtool that is implemented on computing equipment, comprising: with thelink simulation tool, displaying a timing diagram for transmittedsignals having varying signal amplitudes at a given point in thecommunications link; with the link simulation tool, displaying aprobability density function plot that represents a distribution ofsignal amplitude variations in the transmitted signals for thecommunications link; and with the link simulation tool, displaying afirst cumulative density function plot that is only a function ofvoltage and a second cumulative density function plot that is only afunction of time.
 8. The method defined in claim 7, wherein displayingthe timing diagram comprises displaying an eye diagram of thetransmitted signals of the communications link.
 9. The method defined inclaim 7, wherein displaying the probability density function plotcomprises displaying a noise histogram plot for the transmitted signalsfor the communications link.
 10. The method defined in claim 9 furthercomprising: with the link simulation tool, displaying a jitter histogramplot for the transmitted signals for the communications link.
 11. Themethod defined in claim 7 further comprising: with the link simulationtool, displaying a three-dimensional bit error rate plot for thetransmitted signals at the given point in the communications link.
 12. Amethod of simulating a communications link using a link simulation toolimplemented on computing equipment, comprising: with the link simulationtool, providing a user with an opportunity to specify random jitterrequirements for the communications link; with the link simulation tool,providing the user with an opportunity to specify random noiserequirements for the communications link; with the link simulation tool,producing simulation results for the communications link based on therandom jitter and noise requirements specified by the user; and with thelink simulation tool, providing the user with an opportunity to specifya target bit error rate for the communications link.
 13. The methoddefined in claim 12 further comprising: with the link simulation tool,providing the user with an opportunity to specify a data rate for thecommunications link.
 14. The method defined in claim 12, whereinproducing the simulation results comprises displaying jitter and noiseprobability density function plots that are based on the random jitterand noise requirements specified by the user for the communicationslink.
 15. A non-transitory computer-readable storage media forsimulating performance in a communications link, comprising instructionsfor: providing a user with an opportunity to specify link simulationsettings for the communications link; performing two-dimensionalconvolution operations to simulate performance in the communicationslink, wherein the two-dimensional convolution comprises convoluting afirst function that is dependent on time with a second function that isdependent on voltage, wherein the communications link includes atransmitter subsystem that is represented by a transmitter subsystemmodel, and wherein performing the two-dimensional convolution operationscomprises performing two-dimensional convolution operations with thetransmitter subsystem model; and displaying simulation results for thecommunications link produced by performing the two-dimensionalconvolution operations.